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VNF6PECL155 155-MHz Single-Ended and DifferentialECL/PECL-Compatible I/O
Block Diagram
€ 0.6-micron, 5-volt CMOS technology
€ 0.8-voltage swing
€ 190 MHz maximum operating speed
€ 100K ECL level compatible
€ Differential and single-ended output drivers
€ Receiver with differential and
single-ended input capability
€ Current biasing supports multiple transmitters
€ Power down signal for power conservation
€ Selectable 50-ohm or 750-ohm termination
€ 1 ns maximum edge rate
€ 0.3 ns maximum output skew
€ 2 ns maximum propagation delay
The VNF6PECL155 is a family of high-speed I/O telecommunication and networking functional system blocks ideally suited for ATM and SONET/ SDH applications. The VNF6PECL155 aids in interconnecting CMOS ASICs and interfacing CMOS to ECL circuits. The family consists of a single-ended PECL transmitter, a differential PECL transmitter, and a PECL receiver with single-ended and differential capability.
VNF6PHAL155 155-MHz Phase Aligner
Block Diagram
€ Works with data and clock
speeds of up to 190 MHz
€ Removes up to ±3 UI of 100
Hz input jitter
€ Can take up to 65 UI of consecutive
identical digits (CID)
€ Provides a bit slip indicator output
and reset input
€ Utilizes 0.6-micron, 5-volt technology
The VNF6PHAL155 is a monolithic phase aligner functional system block used for synchronizing a high-speed clock and a data stream within an ASIC device. The VNF6PHAL155 is ideally suited for high-speed telecommunication and networking applications such as ATM and SONET/SDH applications.
VNF7PECL155 155-MHz Single-Ended and Differential ECL-Compatible I/O
Block Diagram
€ Low power, 0.5-micron, 3.3-volt CMOS technology
€ 0.8 V voltage swing
€ 200 MHz maximum operating speed
€ ECL level compatible
€ Differential and single-ended
output drivers
€ Receiver with differential
and single-ended input capability
€ Current biasing supports
multiple transmitters
€ Power down signal for power conservation
€ Selectable 50-ohm or 75-ohm termination
€ 1.0 ns maximum edge rate
€ 0.3 ns maximum output skew
€ 1.5 ns maximum propagation delay
The VNF7PECL155 is a family of high-speed I/O telecommunication and networking functional system blocks ideally suited for ATM and SONET/ SDH applications. The VNF7PECL155 aids in interconnecting CMOS ASICs and interfacing CMOS to ECL circuits. The family consists of a single-ended transmitter, a differential transmitter, and a receiver with single-ended and differential capability.
VNS14Q575 T1/E1 Quad Line Interface Unit
€ Four analog PCM line interfaces
for T1 and E1(CEPT) applications
€ Four jitter attenuators, group
selectable for Tx or Rx direction
€ Standard 8-bit microprocessor
interface with separate address,
data, and control buses
€ Supports popular DS1/E1 Framers
€ Plastic surface-mount packaging:
128-pin Plastic
Quad Flat Package (PQFP)
€ Submicron CMOS technology
(725 mW typical, 1.2 W worst-case)
€ Meets Bellcore TR499 and
AT&T 62411 specifications
€ Transmit pulse shaping per DSX-1
pulse template: 0 to 655 feet
€ Transmit pulse shaping per
CCITT G.703 pulse templates
The VNS14Q575 provides a single integrated solution for high-density T1/E1 short-haul transceiver applications. From a single clock, the VNS14Q575 terminates four PCM interfaces. Both DSX-1 (ANSI) or E1/CEPT (CCITT) formats are supported. A microprocessor interface, common to all four transceivers, provides extensive monitoring, loopback, and control capabilities.
Comprehensive monitoring features are included which allows visibility of all critical parameters. Advanced submicron CMOS processing and plastic surface-mount packaging offer substantial savings in power dissipation and system component cost. The VNS14Q575 supports hardware mode operation for implementations with pin-selectable feature control.
VNS67200 ATM QUAD UNI
€ ITU I.432 and ATM Forum 3.1 UNI compliant
€ Provides four full duplex STS-3c/STS-1
serial line interfaces operating at 155/52 Mbps
€ 50-MHz Level 2-compliant UTOPIA
bus interface to the ATM switch provides
independent 16 bit wide transmit and
receive data paths
€ Maps ATM cells into SONET/SDH frames
€ Generic 8-bit microprocessor bus interface
for configuration, control and status monitoring
€ Pseudo-ECL (PECL) level signals at the STS interface
€ 208-pin thermally enhanced PQFP package
The VNS67200 ATM Quad User Network Interface provides an integrated solution to connecting the core logic of an ATM cell switching system to up to four 155.52-Mbps or 51.84-Mbps full duplex serial data communication channels (STS-3c/STS-1 format). External optical line interface and clock recovery circuits permit connection to SONET OC-3 or OC-1 lines. Complete ATM cell delineation (CDB) and SONET Transmission Convergence Sub-Layer (STCS) functionality is provided.
VNS80000 VLSI ISDN Processor
Block Diagram
€ ARM RISC processor running at 36.8 MHz,
with 3 Kbytes of on-chip high-speed
cache SRAM and support of 8/16/32-bit
wide external SRAM/ROM/DRAM
€ On-chip S0-interface transceiver containing
AFE, data/clock recovery and framing
circuitry conforming to the ITU I.430 specification
€ Low-level D-channel data link controller
providing Layer 1 and basic Layer 2
functions in hardware
€ G.711 PCM CODEC, complete with programmable
AFE, tone ringer output, additional input
and output with internal A/D converters for
volume control, etc. Internal 14-bit linear PCM format
€ Industry-standard serial interface (UART),
supporting baud rates from 1.2 K to 115.2 K
€ Standard 64-bit serial DSP/CODEC interface
with switchable master and slave modes
€ Key pad scanner and LED driver with
buffered LCD controller interface
The VNS80000 VLSI ISDN Processor (VIP), offers in a single device a powerful programmable engine for the development of ISDN terminals and ISDN/PC Card communications equipment. It includes all the circuitry required to implement a full-featured ISDN terminal, making it the most highly integrated and cost-effective solution on the market .
Wireless
Geode CDPD Modem Reference Solution Geode CDPD Modem Reference Solution
€ Complete CDPD modem reference solution for
CDPD Mobile End Systems (M-ES)
€ Optimized specifically for CDPD-only
applications such as telemetry, service
dispatch and point-of sale transactions
€ High level of integration minimizes cost,
power, and size of final products
€ Fully tested reference design minimizes
development risk, time, and cost
€ Two chip architecture - Ruby II Advanced
Communication Processor and Topaz™
mixed-signal radio interface
€ Complete CDPD modem reference solution
includes protocol stack software, baseband
circuit reference design, and radio reference design
€ Complete software development tools,
development card, radio, reference design
schematic, layout, Bill of Materials,
software and on-site training facilitate
end-product development
VLSI1s Geode CDPD is a complete modem reference solution targeted at CDPD M-ES applications such as telemetry, service dispatch, and point of sale transactions. The Geode CDPD comprises two chips (Ruby II Advanced Communication Processor and Topaz Radio Interface), complete CDPD software, and reference designs for a baseband circuit and a CDPD radio. VLSI1s Geode has been completely integrated, tested, and validated through on-the-air tests. Customers can use the Geode CDPD reference solution to quickly get to market with their own highly-integrated, cost-effective, low-power M-ES. VLSI1s Geode CDPD minimizes the time and risk associated with designing and certifying a CDPD modem.
GTI-2000 Complete GSM Handset Solution
Block Diagram
€ Size: 120 x 46 x 8 mm, 6 layers, double-side,
single-board PCB integrating complete GSM
hardware including SIM interface for handset
€ Weight: less than 180 gr
€ Volume: under 120 cm3 including batteries
€ Standby time: 48 hrs (5 V solution) 67
hrs for future 3 V technology
€ Talk time: 2.2 to 3.6 hrs depending on
DTX and power control management provided
by the network. (Battery: NiCad 550 mA/hr)
€ Manufacturability & Reliability
(only 2 tuning points and no 0402 components)
Possibility to produce customized layout
The GTI-2000 is a complete GSM handset solution developed by VLSI and Wavecom for licensing to the market. The design is built around the standard building blocks available from both companies, the VP22020/ VP22002 3Two Chip2 chipset from VLSI, and the GSM RF module and GSM software package from Wavecom. Wavecom also offers a complete portfolio of services to the customer for the completion of the final product including support and training up to Full Type Approval (FTA).
VP22002 GSM/PCN Kernel Processor
Block Diagram
€ 13-MHz low-power oscillator
€ VP22020 GSM/PCN Vocoder compatible
€ 176-pin TQFP package
€ Low power:
Dedicated 150 mW at 5 V
Idle: 26 mW at 5 V
Sleep: 0 µW at 5 V
The VP22002 Kernel Processor is the stablemate to the VP22020 Vocoder: together they form VLSI1s 3Two-Chip2 GSM/PCN solution. These two chips alone perform the necessary baseband signal processing required for a GSM & PCN mobile terminal from the speech vocoding to the radio system interface.
The VP22002 implements all the real-time Layer 1 processing in dedicated hardware. The upper software layers including MMI are supported within the embedded RISC processor. This provides a very powerful "kernel" around which to build a fully integrated, low-power, minimum-component GSM handset.
VP22020 GSM/PCN Vocoder
Block Diagram
€ VP22002 GSM/PCN Kernel Processor compatible
€ Power management facilities
€ 13-MHz low-power oscillator
€ 100-pin TQFP package
€ Low power:
Dedicated mode: 85 mW at 5 V, 35 mW at 3 V
Idle Mode: 100 µW
Together with the VP22002 Kernel Processor they form VLSI1s "Two-Chip" solution for GSM & PCN applications. These two chips alone
perform the necessary baseband signal processing required for a GSM and PCN mobile terminal, from the speech vocoding to the radio system interface.
VP23000 DECT Protocol Processor
Block Diagram
€ Implements the digital processing for
DECT physical layer and partial MAC layer
€ Compliant with ETS 300-175
€ G.721 ADPCM transcoding for three voice channels
€ Fully programmable radio interface
€ Host processor interface supports
M37702, H8, 80C196, and others
€ Industry-standard PCM interface
€ RSSI port
€ DTMF tone generator
€ Speech volume control and fast muting
€ DECT encryption
€ Echo canceller port
€ Voltage range: 2.7 V to 5.5 V
€ Low power: 60 mW at 5 V, 40 mW at 3 V
€ 100-pin TQFP package
The VP23000 is a complete digital processing subsystem for the DECT physical layer, and also implements various MAC layer functions. The VP23000 operates as a coprocessor to a variety of microcontrollers to deliver an efficient and flexible DECT solution.
At the heart of the VP23000 is the DECT core. For transmission, it assembles the data for each time slot, adds CRCs, and outputs data serially at the correct position in the frame. During receive, the core synchronizes to the serial bit stream from the radio, extracts the A and B fields, and checks the CRC.
The VP23000 incorporates a software-programmable radio interface, allowing a wide range of radio architectures to be used without the need for glue logic. The integrated G.721 transcoder handles up to three simultaneous voice channels and also supports DTMF tone generation, call progress tone generation and fast muting in response to corrupted speech data.
VP23001 DECT Audio Processor
Block Diagram
€ Implements the digital processing for
DECT physical layer and partial MAC layer
€ Compliant with ETS 300-175
€ G.721 ADPCM transcoding
€ Fully programmable radio interface
including RSSI port
€ Host processor interface supports
M37702, H8, 80C196, and others
€ Extended memory addressing
€ Memory write protection
€ Enhanced handover performance
€ DTMF tone generator
€ Speech volume control and fast muting
€ DECT encryption
€ Echo canceller port
€ Direct LCD icon drive
€ Supports protected Ip B field
format for data applications
€ Voltage range: 2.7 V to 5.5 V
€ Low power: 35 mW at 3 V (typ)
€ 100-pin TQFP package
The VP23001 DECT Audio Processor incorporates all the functions necessary to implement a minimum-component-count, low-power handset. The VP23001 contains a fully-programmable PCM Codec, a complete digital processing subsystem for the DECT physical layer, and a versatile radio interface. A flexible host processor interface allows the VP23001 to operate with a variety of popular processors and microcontrollers to deliver an efficient and flexible DECT solution.
VP23020 8 x G.721 ADPCM Transcoder
Block Diagram
€ Transcodes eight full-duplex channels
€ CCITT Blue Book G.721-compliant
€ Group delay: 125 µs nominal
€ Selectable ADPCM interface timings
€ Selectable PCM and ADPCM input delays
€ PCM interface supports A-law
and µ-law companding
€ Echo canceller interface
supports A-law, µ-law and linear
€ Serial Control Interface
€ Power supply range: 5 V ±10%
€ Power consumption :
280 mW typ. (all channels active)
10 mW max. (all channels idle)
€ 68-pin PLCC or 100-pin TQFP package
The VP23020 octal G721 device is a CCITT Blue Book-compliant transcoder that allows eight full duplex channels to be processed. It incorporates 2.048-MHz interfaces for PCM and ADPCM data, a 2.048-MHz serial interface to connect another device (such as a DSP) for echo cancellation, and a slow serial control interface. Selectable ADPCM interface timings allow many combinations of highways and capacities, with up to four octal G.721 devices attached to common highways without additional logic.
G.721 increases the capacity of 64 kbit/s PCM voice channels by reducing the data rate requirements to 32 kbit/s ADPCM, and has found wide applications in cordless telephony standards such as DECT and CT2 as well as in pair-gain applications where the bearer capacity of a single cable pair is doubled.
VP23030 DECT PBX Processor
Block Diagram
€ Implements the digital processing for
DECT physical layer and partial MAC layer
€ Compliant with ETS 300-175
€ Standard interface to 64-slot ADPCM highway
€ Fully programmable radio interface
€ Remote-radio-head architectures supported
€ Data recovery circuit with digital
fast-slice control
€ Incorporates DECT encryption
€ Integrated RSSI ADC providing
automated RSSI measurement
€ Host processor interface supports
M37702, H8, 80C51 and others
€ Industrial-standard interfaces:
IOM-2 interface chips (ISDN)
PCM interface chips
(VP23020 Octal G.721 transcoder)
€ Supports protected Ip B field format
for data applications
€ Voltage range: 2.7 V to 5.5 V
€ Low power: 40 mW at 5 V, 25 mW at 3 V
€ 100-pin TQFP package
The VP23030 (3Sirius2) is an advanced digital processing subsystem for the DECT Physical Layer, which implements and supports many advanced MAC functions. The VP23030 integrates a powerful ADPCM interface block with a complete digital processing subsystem for the DECT physical layer and a versatile radio interface. A flexible host processor interface allows the VP23030 to operate with a variety of popular microcontrollers to deliver an efficient and flexible DECT solution for a wide variety of PBX, telepoint, and local loop architectures. The VP23030 also incorporates a remote-radio-head interface for large PBX applications.
VPS10101 Ruby II General-Purpose PC Card Controller
Block Diagram
€ ARM core provides industry-leading MIPS/watt
and MIPS/dollar performance
€ Operating frequency up to 32 MHz
€ Integrated peripherals dramatically simplify
PC Card/ISA and embedded application development
€ Low power:
30 mA on-line mode
7.9 mA command mode
1.5 mA sleep mode
150 µA stop mode
(Typical values, based on 20-MHz, 1 wait-state operation.)
€ Available in 176-pin TQFP and 144-pin TQFP
€ Full set of development tools including C compiler,
assembler, graphical debugger, and development card
available for both UNIX and PC platforms
The VPS10101, "Ruby II," is the first commercially available, general-purpose PC Card controller. Ruby II has been designed to meet the demands of portable communication applications, such as PC Card, for which low-power, miniature, low-cost solutions are required. Ruby II1s 32-bit RISC processor and integrated communication interfaces enable system designs, which optimize system performance (MIPS) while minimizing power and cost. PC Card hardware designs often consist of only Ruby II and external memory. Ruby II applications include wireless LAN, data security, CDPD, embedded control, and modems.
Computing
VCF94100 PCI Functional System Block
Block Diagram
€ Fully compatible with PCI Local
Bus Specifications, revision 2.0
€ 32-bit Master/Slave PCI implementation
€ Separate PCI (0 to 33 MHz) and Local clock (0 to 50 MHz)
€ Supports up to eight peripheral functions
€ Internal master DMA engine
€ Master/Slave read and write
operation in memory, I/O and configuration address space
€ PCI parity generation, checking and error reporting
€ Configuration Space: Supports
access to customer defined configuration
space through internal bus interface
€ Internal Bus Interface:
Separate 32-bit data and address bus
Pipelined base address select output(s)
for fast slave burst operations
€ VHDL technology-independent implementation
The VCF94100 is a functional system block element that implements a Peripheral Component Interconnect (PCI) Master/Slave Interface. The VCF94100 is fully compatible with PCI Local Bus Specification Revision 2.0. The VCF94100 supports a PCI clock rate from 0 to 33 MHz, 32-bit PCI interface with optional 64-bit internal addresses, master/slave burst reads and writes in memory, I/O and configuration space. VCF94100 PCI FSB element is a highly integrated, value-added, standard function that is easily integrated as part of an ASIC or ASSP device. The VCF94100 is designed in VHDL and technology independent. The VHDL source code is highly configurable prior to synthesis. Only the functionality required by an application is synthesized. Verilog development is supported with a structural netlist.
VCF94200 SSA Functional System Block
Block Diagram
€ Fully compatible with Serial Storage
Architecture SSA-PH Specification,
Revision 01 (ANSI X3T 10)
€ Register and buffer level compatible
with IBM Serial Interface Chip (SIC)
€ Fully integrated-dual port configuration
€ 20 Mbyte/s data transfer rate
(40 MBytes/s in Full Duplex mode)
€ Supports string, loop and switched
SSA network
€ Low latency cut-through routing
supported in paired ports and
for automatic switching mode operation
€ High degree of data integrity checking
with parity checking on internal buses
and Vertical Redundancy Checking (VRC)
on internal buffers
€ Dual inbound and outbound frame
buffering control logic
€ Supports single-port, dual-port
and switched SSA nodes
€ High fault coverage testability
with built-in scan test capability
€ Separate control register, Frame Status
Register (FSR) and buffer data paths
€ Full SSA Channel supports for
0 to 16,256 Channels
€ Supports VHDL and Verilog
The VCF94200 is a functional systems block element that implements a dual-ported Serial Storage Architecture (SSA) interface. SSA is a high-performance serial interface for connecting storage devices in storage sub-systems, servers, and workstations. SSA FSB elements are highly integrated, value-added, standard functions that are easily integrated as a part of an ASIC or ASSP device. The VCF94200 SSA FSB implements the complete SSA protocol as defined by the SSA-PH Specification, Revision 01(ANSI X3T10.1).
VCS94250 PCI/SSA I/O Processor
Block Diagram
€ 0-33 MHz, 32-bit master/slave PCI interface
€ Embedded, 32-bit ARM RISC processor operating at 25 MHz
€ Multi-channel DMA engine
€ 4 KByte SRAM for ARM control
store and DMA channels
€ DMA Controller transfers SSA frames
concurrently with ARM processor operations
€ Fully compatible with PCI Local
Bus Specification, Revision 2.0
€ Synchronizes external 0-33 MHz
PCI bus transactions with internal
50-MHz transactions
€ Supports selection of external
PCI BIOS ROM size from 16K Bytes to 4M Bytes
€ 5 volt tolerant, 3.3 volt I/O
€ Fully compatible with Serial
Storage Architecture (SSA) specifications
€ Register-level and buffer-level
compatible with IBM Serial Interface Chip (SIC)
€ 20 MBytes/sec full-duplex operation per port
The VCS94250 PCI/SSA I/O Processor is a single chip for integrating the Serial Storage Architecture (SSA) interface into host systems with a Peripheral Component Interconnect (PCI) Local Bus.
The VCS94250 provides a PCI/SSA solution with an excellent combination of very high performance, integration, flexibility, reliability, compatibility, and value. SSA is a serial interface for connecting storage devices in storage sub-systems, servers, and workstations. PCI is a multiplexed address/data bus for connecting peripheral components and peripheral add-in boards in personal computers, workstations, and many types of embedded systems.
VCS94450 IR Communication Controller (IrCC)
€ IR Subsystem which includes:
(1) One 85C30 SCC
(2) Two 16550 UARTs
(3) IR Logic
€ Compatible with the IrDA 2.0
standard (IR transmission speed 1.15 Mbps)
€ ISA Interface: Compatible with
the VLSI PCMCIA FSB with minor modifications
€ 16-deep FIFO for transmit and receive,
data buffering and DMA capability
€ 16-bit address bus and 8-bit data bus
€ Programmable Option Select (POS)
registers during setup
€ IR Modem: Supports different
modulation/demodulation schemes
€ Others: Gain control of IR transmit
and receive signals, IR power down mode
€ 36.846-MHz clock
€ Available in 100-pin TQFP (Thin Quad Flat Pack)
The highly integrated IR Communication Controller (IrCC) supports communication between the IR-communication link, printer parallel port, PCMCIA interface, ISA interface, external modem, and a pass through function from the host. The IrCC can be used as a standard product with the capability to customize using FSB's and customer- defined logic.
The IR subsystem is designed using two industry-standard16550 UARTs for asynchronous communication, a mono-channel 85C30 SCC FSB for high-speed synchronous communications, and a register set which provides setup and control of various modes. The 16550 UART and the 85C30 SCC are fully compatible with National Semiconductor 16550 UART and Zilog Z85C30 SCC.
The IR subsystem has the ability to connect with both host-driven and modem-driven RS232 asynchronous interfaces. ICC supports both the IBM and HP modes of operation.
VL82C530 Eagle Ð 586-Class Processor Solution
Block Diagram
€ Highly integrated PCI chipset
and PCI peripheral devices packaged in low-profile BGAs
Supports Pentium and Pentium-class CPUs
64-bit wide EDO DRAM controller
33 MHz asynchronous PCI local bus
€ Industry standard power-managed
PCI super I/O controller;
fully buffered FAST IDE controller;
integrated floppy disk controller;
two UARTS; 8051 keyboard controller;
integrated clock generators; ECP Port;
infrared communications port; RTC;
two PWM outputs
€ PCI to PCI bridge to enable
PCI docking
€ PCI to ISA bridge to enable
ISA in the docking station
VL82C530 Eagle is VLSI1s latest system solution optimized for the expanding mobile Pentium™ market. Carrying forward VLSI1s mobile strategy to offer a complete solution, Eagle soars forward and integrates the chipset into a single Ball Grid Array (BGA) package. Also included is a tightly-coupled PCI Super I/O controller that integrates all the standard mobile peripherals. In addition, a pair of PCI bridges are included to enable high-speed, buffered PCI docking and to enable a full-featured ISA bus in the docking station.
VL82C541 and VL82C543 Lynx 586-Class Desktop System Solution
€ Two-chip solution allows efficient
use of board space
€ 352-lead PBGA (Plastic Ball Grid Array)
€ Lynx system controller
€ 208-lead MQFP (Metric Quad Flat Pack)
€ Lynx ISA controller
€ Supports two signal layer board routing
€ Supports up to 66-MHz CPU clock speed
€ Supports Pentium, M1, and K5 CPUs
€ Supports 3.3 V or 5 V DRAM
€ Supports complete distributed
DMA protocol
€ Supports 33-MHz PCI bus operation,
independent of CPU bus speed
€ Compatible with PCI local
bus specification (Rev 2.1)
The Lynx chip set is VLSI1s third-generation solution for the 586-class desktop market. Lynx charges ahead by offering a two-chip set with lightning-fast performance, continuing VLSI1s strategy of offering cost-optimized, high-performance solutions. The Lynx chipset demonstrates VLSI1s ongoing quest for system performance via multi-level system concurrency, increased integration, advanced distributed DMA architecture, and integrated bus mastering IDE.
VL82C594, VL82C595 and VL82C596/597 Wildcat 586-Class PCI Chipset
€ Supports P5, P54C, P54CS,
P55C, K5, and M1 CPUs
€ Dual processor option
supporting Intel CPUs
€ Supports up to eight SIMM
sockets of FPM or EDO DRAM
€ Integrated L2 cache supports
async, sync, or PBSRAM
€ Power management features
support 3Green PC2 operation
Wildcat is a 586-class PCI chipset comprised of the VL82C594 System Controller, two VL82C595 Data Buffers, and the VL82C596/VL82C597 ISA Bridge. The VL82C596 is for single processor systems using a P5, P54C, P54CS, P55C, K5, or M1 CPU. The VL82C597 includes the Intel IO APIC for use in Intel-based dual processor systems. The VL82C594 supports up to 1G of fast page mode or EDO DRAM. It also supports up to 1M of async, sync, or PBSRAM. The VL82C595 data buffers work with the VL82C594 to provide 3smart2 write buffering to yield exceptional performance with or without an L2 cache. The VL82C596/597 acts as a PCI-ISA bridge and incorporates advanced power management features and a Real-Time Clock with integrated write protection.
VL82C925 Mobile RISC Graphics Accelerator
€ Single-chip PCI LCD controller with
integrated true-color RAMDAC and
ual clock synthesizers
€ Accelerated Super VGA modes utilizing
a configurable geometry pipeline with
BLT, ROP, and accelerated graphics text support
€ Support for EDO, SDRAM, and SGRAM up to 4 MB
€ Progressive Power Management
VESA DPMS and DDL support
Auto Clock System autonomic power management
RAM self-refresh and clock enable control
€ CRT resolution up to 1024 x 768 x 64K
colors at 75 Hz (non-IL)
€ TFT or dual scan STN LCD support
640 x 480 monochrome STN, 64 gray shades
800 x 600 color STN with
4K colors (high resolution)
800 x 600 color STN with
256K colors (low resolution)
800 x 600 color TFT with 256K colors
Simultaneous display of CRT with LCD modes
€ Configurable hardware cursor
with overlay/pop-up
€ Software compatible to all
VL82C9xx graphics products
The VL82C925 is the first in a family of mobile RISC Graphics accelerators based on VLSI1s GraphiCore™ architecture. At the core of the graphics engine is a variable width accelerator designed by VLSI engineers to achieve high panel and display resolutions with single-state execution and progressive power management.
VL82C975 Desktop RISC Graphics Accelerator
Block Diagram
€ Single-chip Super VGA PCI accelerator
with integrated dual clock synthesizers
€ Configurable geometry pipeline with BLT,
ROP, and accelerated graphics text support
€ Support for 4 MB EDO SDRAM, SGRAM, AND VRAM
€ Fast linear frame buffer access up to 4 MB
€ Progressive power management
VESA DPMS and DDC support
Auto Clock System autonomic power management
RAM self-refresh and clock enable control
€ Supports a 16-bit VESA Advanced Feature Connector
€ CRT res. up to 1280 x 1024 x 256 colors
at 75 Hz (non-IL)
1280 x 1024 x 16M pseudo true color
at 75 Hz (non-IL)
1024 x 768 x 64K colors at 75 Hz (non-IL)
800 x 600 x 16M colors at 75 Hz (non-IL)
€ 8- or 16-bit RAMDAC port allows selectability
of DAC features
€ Configurable hardware cursor
€ Pin-to-pin compatible with the VL82950
€ Software-compatible to all VL82C9xx
graphics products
The VL82C975 is the first in a family of desktop RISC Graphics accelerators based on VLSI1s Graphicore architecture. At the core of the graphics engine is a variable width accelerator designed to achieve high display resolutions with single-state execution. In addition, the VL82C975 offers color depth conversion to display true color images with as little as one-third the normal storage requirement.
Entertainment
VES2020 MPEG 2 Transport Demultiplexer
Block Diagram
Data Sheet
€ Handles MPEG 2 Transport and Packetized
Elementary Stream (PES) Layers up to 60 Mbps
€ Performs Program Clock Reference (PCR) recovery
€ Program-Specific Information (PSI)
and Program Time Stamp (PTS) management
€ Channel rate buffering for video,
audio, and host microcontroller
€ Shared DRAM memory controller for demux,
host microcontroller, and MPEG audio decoder
€ Descrambler interface
€ I2C bus master support
The VES2020 MPEG 2 Transport Stream Demultiplexer handles MPEG 2 transport streams and Packetized Elementary Streams (PES) of up to 60 Mbps, parses the streams to frame the MPEG 2 packets, and then routes the extracted packets to either an MPEG 2 video decoder, MPEG audio decoder, or to a host microcontroller for downstream processing. The VES2020 also performs Program Clock Reference (PCR) recovery to maintain audio and video synchronization, acts as the DRAM memory controller for not only itself, but also for the host microcontroller and MPEG audio decoder, thus reducing overall system DRAM requirements and cost. The VES2020 comes with necessary firmware, and is packaged either in a 160- or 208-lead MQFP package.
VES4113 QAM Digital Demodulator
Block Diagram
Data Sheet
€ 16, 32, 64, 128, and 256 QAM demodulation
€ Operates up to 28 MHz, with
modulation rates up to 7 Mbaud
€ Carrier acquisition range up
to ±8% of symbol rate
€ DVB-compliant
€ Automatic gain control (AGC) output
€ Digital 9-bit bandpass input signal
€ Digital down conversion
€ Symbol timing recovery
€ Fully digital carrier recovery loop
€ Integrated adaptive equalizer
(transversal or DFE)
€ Blind equalization for rapid
carrier recovery synchronization
€ I2C bus interface
€ 68-PLCC package
The VES4113 is a DVB-compliant digital demodulator for 16, 32, 64, 128, or 256 QAM modulated signals. The device interfaces directly to the bandpass input signal, following 9-bit A/D conversion at four times the symbol rate. The VES4113 provides a feedback signal to control the sampling clock via an external VCXO and includes the carrier recovery function. The internal digital loop filters for both clock and carrier recovery are programmable to permit optimization according to the application. The VES4113 operates up to 28 MHz, can be directly connected to the VES5453 FEC decoder, and comes in a 68-lead PLCC package.
VES4143 Variable-Rate QPSK Digital Demodulator
Block Diagram
Data Sheet
€ Supports modulation rates
up to 30 MBaud
€ DVB-compliant
€ Automatic gain control outputs
€ Symbol timing recovery
acquisition range of ±100 ppm
€ Carrier recovery with acquisition
range of ± modulation rate
€ Input and output format selectable
to either two's-complement or
offset-binary format
€ On-chip DC offset compensation
€ Integrated half-Nyquist
baseband filters (a = 0.35)
€ Operates at low Eb/No (> - 1 dB)
€ I2C bus interface
€ BER performance within
0.5 dB typical of ideal uncoded
The VES4143 is a DVB-compliant variable-rate digital demodulator for BSPK and QPSK modulated signals. The device directly interfaces to I and Q digital baseband signals following down conversion. The center frequency, at twice the modulation rate, is programmable via the I2C interface and is internally tuned by the clock recovery circuitry. The carrier recovery function requires no feedback loop control from the IF local oscillator, decreasing overall system component cost. The VES4143 operates at speeds up to 60 MHz with modulation rates of up to 30 Mbaud, interfaces directly with the VES5453X FEC decoder, and is available in a 68-lead PLCC package.
VES4613 QED 64/256 -QAM Subsystem
Block Diagram
€ 64/256 QAM demodulation
€ Provides robust performance of
up to 43.2 Mbps in a 6-MHz bandwidth
channel under even highly impaired conditions
€ AGC control and AM-hum removal
€ Performs quadrature downconversion
€ Symbol timing and carrier recovery
€ Blind equalization
€ Low-cost system implementation
Utilizes standard IF at 43.75 MHz
Standard AGC and SAW BPF
Single ADC
No external VCXOs
€ Performance within 1 dB of theory at 10-5 BER
The VES4613, codeveloped by Applied Signal Technology and VLSI Technology, implements all of the required functions for all-digital quadrature-downconversion, equalization, and demodulation of 64 or 256 QAM for CATV-based applications. This devices operates at a 43.75-MHz IF from inexpensive, off-the-shelf analog-CATV tuners, and demodulates symbol rates of up to 5.4 MBaud, compatible with proposed U.S. digital CATV implementations. The VES4613 is available in a 68-lead PLCC package.
VES5453 High-Speed FEC Decoder
Block Diagram
Data Sheet
€ DVB-compliant Viterbi concatenated
Reed-Solomon with de-interleaving and descrambling
€ Data rates up to R x 60 Mbits/s (R = Viterbi rate)
€ Viterbi decoder:
- Supports rates of 1/2, 2/3, 3/4,
4/5, 5/6, 6/7, 7/8, and 8/9
- Automatic de-puncturing and
bit synchronization
€ Reed-Solomon decoder:
- N = 204, K = 188, t = 8,
symbol width = 8 bits
€ Forney convolutional de-interleaving
of depth 12
€ Automatic frame synchronization
€ Descrambling to IESS 309 / DVB
specifications
€ I2C bus interface
The VES5453 is a single-chip forward error correction (FEC) decoder for digital broadcast satellite and cable television receivers. The VES5453 features Viterbi concatenated Reed-Solomon decoders with de-interleaving and descrambling. The algorithms implemented improve coding gain for punctured codes and are fully DVB-compliant. Automatic synchronization of the de-interleaver and the Reed-Solomon decoder is provided. The VES5453 includes an I2C bus interface for easy configuration and control. The I and Q inputs to the VES5453 can be connected directly to the VES4123 or VES4143 QPSK digital demodulator outputs, and the device comes in a 68-lead PLC package.